//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Tue May 16 15:28:10 2023
//Host        : DESKTOP-TJ8OSUQ running 64-bit major release  (build 9200)
//Command     : generate_target pcie_system_wrapper.bd
//Design      : pcie_system_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module pcie_system_wrapper
   (BRAM_PORTA_addr,
    BRAM_PORTA_clk,
    BRAM_PORTA_din,
    BRAM_PORTA_dout,
    BRAM_PORTA_en,
    BRAM_PORTA_rst,
    BRAM_PORTA_we,
    DDR3_addr,
    DDR3_ba,
    DDR3_cas_n,
    DDR3_ck_n,
    DDR3_ck_p,
    DDR3_cke,
    DDR3_cs_n,
    DDR3_dm,
    DDR3_dq,
    DDR3_dqs_n,
    DDR3_dqs_p,
    DDR3_odt,
    DDR3_ras_n,
    DDR3_reset_n,
    DDR3_we_n,
    DDR_addr,
    DDR_ba,
    DDR_cas_n,
    DDR_ck_n,
    DDR_ck_p,
    DDR_cke,
    DDR_cs_n,
    DDR_dm,
    DDR_dq,
    DDR_dqs_n,
    DDR_dqs_p,
    DDR_odt,
    DDR_ras_n,
    DDR_reset_n,
    DDR_we_n,
    FCLK0_OUT,
    FIXED_IO_ddr_vrn,
    FIXED_IO_ddr_vrp,
    FIXED_IO_mio,
    FIXED_IO_ps_clk,
    FIXED_IO_ps_porb,
    FIXED_IO_ps_srstb,
    GPIO_I,
    GPIO_O,
    GPIO_T,
    IIC_scl_io,
    IIC_sda_io,
    PS_FRSTN0,
    SPI0_MISO_I_0,
    SPI0_MOSI_I_0,
    SPI0_MOSI_O_0,
    SPI0_SCLK_I_0,
    SPI0_SCLK_O_0,
    SPI0_SS1_O_0,
    SPI0_SS2_O_0,
    SPI0_SS_I_0,
    SPI0_SS_O_0,
    UART_1_0_rxd,
    UART_1_0_txd,
    clk_100M,
    clk_200M,
    clk_out_0,
    dac_data_0,
    dac_valid_0,
    enable_0,
    enable_1,
    fdma_rstn,
    idly_d_0,
    idly_en_0,
    init_calib_complete,
    packed_fifo_wr_data_0,
    packed_fifo_wr_en_0,
    packed_fifo_wr_overflow_0,
    packed_fifo_wr_sync_0,
    pcie_mgt_rxn,
    pcie_mgt_rxp,
    pcie_mgt_txn,
    pcie_mgt_txp,
    pcie_ref_clk_n,
    pcie_ref_clk_p,
    pcie_rst_n,
    peripheral_aresetn_0_0,
    pkg_rd_addr,
    pkg_rd_areq,
    pkg_rd_data,
    pkg_rd_en,
    pkg_rd_last,
    pkg_rd_size,
    pkg_wr_addr,
    pkg_wr_areq,
    pkg_wr_data,
    pkg_wr_en,
    pkg_wr_last,
    pkg_wr_size,
    rx1_atten_0,
    rx1_b_atten_0,
    rx_clk_in_n_0,
    rx_clk_in_n_1,
    rx_clk_in_p_0,
    rx_clk_in_p_1,
    rx_data_in_n_0,
    rx_data_in_n_1,
    rx_data_in_p_0,
    rx_data_in_p_1,
    rx_frame_in_n_0,
    rx_frame_in_n_1,
    rx_frame_in_p_0,
    rx_frame_in_p_1,
    s_axis_ready_0,
    temp_out,
    tx1_atten_0,
    tx1_b_atten_0,
    tx_clk_out_n_0,
    tx_clk_out_n_1,
    tx_clk_out_p_0,
    tx_clk_out_p_1,
    tx_data_out_n_0,
    tx_data_out_n_1,
    tx_data_out_p_0,
    tx_data_out_p_1,
    tx_frame_out_n_0,
    tx_frame_out_n_1,
    tx_frame_out_p_0,
    tx_frame_out_p_1,
    txnrx_0,
    txnrx_1,
    ui_clk,
    up_enable_0,
    up_enable_1,
    up_txnrx_0,
    up_txnrx_1,
    user_lnk_up,
    usr_irq_req_0);
  output [12:0]BRAM_PORTA_addr;
  output BRAM_PORTA_clk;
  output [31:0]BRAM_PORTA_din;
  input [31:0]BRAM_PORTA_dout;
  output BRAM_PORTA_en;
  output BRAM_PORTA_rst;
  output [3:0]BRAM_PORTA_we;
  output [14:0]DDR3_addr;
  output [2:0]DDR3_ba;
  output DDR3_cas_n;
  output [0:0]DDR3_ck_n;
  output [0:0]DDR3_ck_p;
  output [0:0]DDR3_cke;
  output [0:0]DDR3_cs_n;
  output [3:0]DDR3_dm;
  inout [31:0]DDR3_dq;
  inout [3:0]DDR3_dqs_n;
  inout [3:0]DDR3_dqs_p;
  output [0:0]DDR3_odt;
  output DDR3_ras_n;
  output DDR3_reset_n;
  output DDR3_we_n;
  inout [14:0]DDR_addr;
  inout [2:0]DDR_ba;
  inout DDR_cas_n;
  inout DDR_ck_n;
  inout DDR_ck_p;
  inout DDR_cke;
  inout DDR_cs_n;
  inout [3:0]DDR_dm;
  inout [31:0]DDR_dq;
  inout [3:0]DDR_dqs_n;
  inout [3:0]DDR_dqs_p;
  inout DDR_odt;
  inout DDR_ras_n;
  inout DDR_reset_n;
  inout DDR_we_n;
  output FCLK0_OUT;
  inout FIXED_IO_ddr_vrn;
  inout FIXED_IO_ddr_vrp;
  inout [53:0]FIXED_IO_mio;
  inout FIXED_IO_ps_clk;
  inout FIXED_IO_ps_porb;
  inout FIXED_IO_ps_srstb;
  input [63:0]GPIO_I;
  output [63:0]GPIO_O;
  output [63:0]GPIO_T;
  inout IIC_scl_io;
  inout IIC_sda_io;
  output PS_FRSTN0;
  input SPI0_MISO_I_0;
  input SPI0_MOSI_I_0;
  output SPI0_MOSI_O_0;
  input SPI0_SCLK_I_0;
  output SPI0_SCLK_O_0;
  output SPI0_SS1_O_0;
  output SPI0_SS2_O_0;
  input SPI0_SS_I_0;
  output SPI0_SS_O_0;
  input UART_1_0_rxd;
  output UART_1_0_txd;
  output clk_100M;
  output clk_200M;
  output clk_out_0;
  input [63:0]dac_data_0;
  input dac_valid_0;
  output enable_0;
  output enable_1;
  output [0:0]fdma_rstn;
  output [4:0]idly_d_0;
  output [6:0]idly_en_0;
  output init_calib_complete;
  output [63:0]packed_fifo_wr_data_0;
  output packed_fifo_wr_en_0;
  input packed_fifo_wr_overflow_0;
  output packed_fifo_wr_sync_0;
  input [3:0]pcie_mgt_rxn;
  input [3:0]pcie_mgt_rxp;
  output [3:0]pcie_mgt_txn;
  output [3:0]pcie_mgt_txp;
  input [0:0]pcie_ref_clk_n;
  input [0:0]pcie_ref_clk_p;
  input pcie_rst_n;
  output [0:0]peripheral_aresetn_0_0;
  input [31:0]pkg_rd_addr;
  input pkg_rd_areq;
  output [127:0]pkg_rd_data;
  output pkg_rd_en;
  output pkg_rd_last;
  input [31:0]pkg_rd_size;
  input [31:0]pkg_wr_addr;
  input pkg_wr_areq;
  input [127:0]pkg_wr_data;
  output pkg_wr_en;
  output pkg_wr_last;
  input [31:0]pkg_wr_size;
  output [31:0]rx1_atten_0;
  output [31:0]rx1_b_atten_0;
  input rx_clk_in_n_0;
  input rx_clk_in_n_1;
  input rx_clk_in_p_0;
  input rx_clk_in_p_1;
  input [5:0]rx_data_in_n_0;
  input [5:0]rx_data_in_n_1;
  input [5:0]rx_data_in_p_0;
  input [5:0]rx_data_in_p_1;
  input rx_frame_in_n_0;
  input rx_frame_in_n_1;
  input rx_frame_in_p_0;
  input rx_frame_in_p_1;
  output s_axis_ready_0;
  output [11:0]temp_out;
  output [31:0]tx1_atten_0;
  output [31:0]tx1_b_atten_0;
  output tx_clk_out_n_0;
  output tx_clk_out_n_1;
  output tx_clk_out_p_0;
  output tx_clk_out_p_1;
  output [5:0]tx_data_out_n_0;
  output [5:0]tx_data_out_n_1;
  output [5:0]tx_data_out_p_0;
  output [5:0]tx_data_out_p_1;
  output tx_frame_out_n_0;
  output tx_frame_out_n_1;
  output tx_frame_out_p_0;
  output tx_frame_out_p_1;
  output txnrx_0;
  output txnrx_1;
  output ui_clk;
  input up_enable_0;
  input up_enable_1;
  input up_txnrx_0;
  input up_txnrx_1;
  output user_lnk_up;
  input [1:0]usr_irq_req_0;

  wire [12:0]BRAM_PORTA_addr;
  wire BRAM_PORTA_clk;
  wire [31:0]BRAM_PORTA_din;
  wire [31:0]BRAM_PORTA_dout;
  wire BRAM_PORTA_en;
  wire BRAM_PORTA_rst;
  wire [3:0]BRAM_PORTA_we;
  wire [14:0]DDR3_addr;
  wire [2:0]DDR3_ba;
  wire DDR3_cas_n;
  wire [0:0]DDR3_ck_n;
  wire [0:0]DDR3_ck_p;
  wire [0:0]DDR3_cke;
  wire [0:0]DDR3_cs_n;
  wire [3:0]DDR3_dm;
  wire [31:0]DDR3_dq;
  wire [3:0]DDR3_dqs_n;
  wire [3:0]DDR3_dqs_p;
  wire [0:0]DDR3_odt;
  wire DDR3_ras_n;
  wire DDR3_reset_n;
  wire DDR3_we_n;
  wire [14:0]DDR_addr;
  wire [2:0]DDR_ba;
  wire DDR_cas_n;
  wire DDR_ck_n;
  wire DDR_ck_p;
  wire DDR_cke;
  wire DDR_cs_n;
  wire [3:0]DDR_dm;
  wire [31:0]DDR_dq;
  wire [3:0]DDR_dqs_n;
  wire [3:0]DDR_dqs_p;
  wire DDR_odt;
  wire DDR_ras_n;
  wire DDR_reset_n;
  wire DDR_we_n;
  wire FCLK0_OUT;
  wire FIXED_IO_ddr_vrn;
  wire FIXED_IO_ddr_vrp;
  wire [53:0]FIXED_IO_mio;
  wire FIXED_IO_ps_clk;
  wire FIXED_IO_ps_porb;
  wire FIXED_IO_ps_srstb;
  wire [63:0]GPIO_I;
  wire [63:0]GPIO_O;
  wire [63:0]GPIO_T;
  wire IIC_scl_i;
  wire IIC_scl_io;
  wire IIC_scl_o;
  wire IIC_scl_t;
  wire IIC_sda_i;
  wire IIC_sda_io;
  wire IIC_sda_o;
  wire IIC_sda_t;
  wire PS_FRSTN0;
  wire SPI0_MISO_I_0;
  wire SPI0_MOSI_I_0;
  wire SPI0_MOSI_O_0;
  wire SPI0_SCLK_I_0;
  wire SPI0_SCLK_O_0;
  wire SPI0_SS1_O_0;
  wire SPI0_SS2_O_0;
  wire SPI0_SS_I_0;
  wire SPI0_SS_O_0;
  wire UART_1_0_rxd;
  wire UART_1_0_txd;
  wire clk_100M;
  wire clk_200M;
  wire clk_out_0;
  wire [63:0]dac_data_0;
  wire dac_valid_0;
  wire enable_0;
  wire enable_1;
  wire [0:0]fdma_rstn;
  wire [4:0]idly_d_0;
  wire [6:0]idly_en_0;
  wire init_calib_complete;
  wire [63:0]packed_fifo_wr_data_0;
  wire packed_fifo_wr_en_0;
  wire packed_fifo_wr_overflow_0;
  wire packed_fifo_wr_sync_0;
  wire [3:0]pcie_mgt_rxn;
  wire [3:0]pcie_mgt_rxp;
  wire [3:0]pcie_mgt_txn;
  wire [3:0]pcie_mgt_txp;
  wire [0:0]pcie_ref_clk_n;
  wire [0:0]pcie_ref_clk_p;
  wire pcie_rst_n;
  wire [0:0]peripheral_aresetn_0_0;
  wire [31:0]pkg_rd_addr;
  wire pkg_rd_areq;
  wire [127:0]pkg_rd_data;
  wire pkg_rd_en;
  wire pkg_rd_last;
  wire [31:0]pkg_rd_size;
  wire [31:0]pkg_wr_addr;
  wire pkg_wr_areq;
  wire [127:0]pkg_wr_data;
  wire pkg_wr_en;
  wire pkg_wr_last;
  wire [31:0]pkg_wr_size;
  wire [31:0]rx1_atten_0;
  wire [31:0]rx1_b_atten_0;
  wire rx_clk_in_n_0;
  wire rx_clk_in_n_1;
  wire rx_clk_in_p_0;
  wire rx_clk_in_p_1;
  wire [5:0]rx_data_in_n_0;
  wire [5:0]rx_data_in_n_1;
  wire [5:0]rx_data_in_p_0;
  wire [5:0]rx_data_in_p_1;
  wire rx_frame_in_n_0;
  wire rx_frame_in_n_1;
  wire rx_frame_in_p_0;
  wire rx_frame_in_p_1;
  wire s_axis_ready_0;
  wire [11:0]temp_out;
  wire [31:0]tx1_atten_0;
  wire [31:0]tx1_b_atten_0;
  wire tx_clk_out_n_0;
  wire tx_clk_out_n_1;
  wire tx_clk_out_p_0;
  wire tx_clk_out_p_1;
  wire [5:0]tx_data_out_n_0;
  wire [5:0]tx_data_out_n_1;
  wire [5:0]tx_data_out_p_0;
  wire [5:0]tx_data_out_p_1;
  wire tx_frame_out_n_0;
  wire tx_frame_out_n_1;
  wire tx_frame_out_p_0;
  wire tx_frame_out_p_1;
  wire txnrx_0;
  wire txnrx_1;
  wire ui_clk;
  wire up_enable_0;
  wire up_enable_1;
  wire up_txnrx_0;
  wire up_txnrx_1;
  wire user_lnk_up;
  wire [1:0]usr_irq_req_0;

  IOBUF IIC_scl_iobuf
       (.I(IIC_scl_o),
        .IO(IIC_scl_io),
        .O(IIC_scl_i),
        .T(IIC_scl_t));
  IOBUF IIC_sda_iobuf
       (.I(IIC_sda_o),
        .IO(IIC_sda_io),
        .O(IIC_sda_i),
        .T(IIC_sda_t));
  pcie_system pcie_system_i
       (.BRAM_PORTA_addr(BRAM_PORTA_addr),
        .BRAM_PORTA_clk(BRAM_PORTA_clk),
        .BRAM_PORTA_din(BRAM_PORTA_din),
        .BRAM_PORTA_dout(BRAM_PORTA_dout),
        .BRAM_PORTA_en(BRAM_PORTA_en),
        .BRAM_PORTA_rst(BRAM_PORTA_rst),
        .BRAM_PORTA_we(BRAM_PORTA_we),
        .DDR3_addr(DDR3_addr),
        .DDR3_ba(DDR3_ba),
        .DDR3_cas_n(DDR3_cas_n),
        .DDR3_ck_n(DDR3_ck_n),
        .DDR3_ck_p(DDR3_ck_p),
        .DDR3_cke(DDR3_cke),
        .DDR3_cs_n(DDR3_cs_n),
        .DDR3_dm(DDR3_dm),
        .DDR3_dq(DDR3_dq),
        .DDR3_dqs_n(DDR3_dqs_n),
        .DDR3_dqs_p(DDR3_dqs_p),
        .DDR3_odt(DDR3_odt),
        .DDR3_ras_n(DDR3_ras_n),
        .DDR3_reset_n(DDR3_reset_n),
        .DDR3_we_n(DDR3_we_n),
        .DDR_addr(DDR_addr),
        .DDR_ba(DDR_ba),
        .DDR_cas_n(DDR_cas_n),
        .DDR_ck_n(DDR_ck_n),
        .DDR_ck_p(DDR_ck_p),
        .DDR_cke(DDR_cke),
        .DDR_cs_n(DDR_cs_n),
        .DDR_dm(DDR_dm),
        .DDR_dq(DDR_dq),
        .DDR_dqs_n(DDR_dqs_n),
        .DDR_dqs_p(DDR_dqs_p),
        .DDR_odt(DDR_odt),
        .DDR_ras_n(DDR_ras_n),
        .DDR_reset_n(DDR_reset_n),
        .DDR_we_n(DDR_we_n),
        .FCLK0_OUT(FCLK0_OUT),
        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
        .FIXED_IO_mio(FIXED_IO_mio),
        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
        .GPIO_I(GPIO_I),
        .GPIO_O(GPIO_O),
        .GPIO_T(GPIO_T),
        .IIC_scl_i(IIC_scl_i),
        .IIC_scl_o(IIC_scl_o),
        .IIC_scl_t(IIC_scl_t),
        .IIC_sda_i(IIC_sda_i),
        .IIC_sda_o(IIC_sda_o),
        .IIC_sda_t(IIC_sda_t),
        .PS_FRSTN0(PS_FRSTN0),
        .SPI0_MISO_I_0(SPI0_MISO_I_0),
        .SPI0_MOSI_I_0(SPI0_MOSI_I_0),
        .SPI0_MOSI_O_0(SPI0_MOSI_O_0),
        .SPI0_SCLK_I_0(SPI0_SCLK_I_0),
        .SPI0_SCLK_O_0(SPI0_SCLK_O_0),
        .SPI0_SS1_O_0(SPI0_SS1_O_0),
        .SPI0_SS2_O_0(SPI0_SS2_O_0),
        .SPI0_SS_I_0(SPI0_SS_I_0),
        .SPI0_SS_O_0(SPI0_SS_O_0),
        .UART_1_0_rxd(UART_1_0_rxd),
        .UART_1_0_txd(UART_1_0_txd),
        .clk_100M(clk_100M),
        .clk_200M(clk_200M),
        .clk_out_0(clk_out_0),
        .dac_data_0(dac_data_0),
        .dac_valid_0(dac_valid_0),
        .enable_0(enable_0),
        .enable_1(enable_1),
        .fdma_rstn(fdma_rstn),
        .idly_d_0(idly_d_0),
        .idly_en_0(idly_en_0),
        .init_calib_complete(init_calib_complete),
        .packed_fifo_wr_data_0(packed_fifo_wr_data_0),
        .packed_fifo_wr_en_0(packed_fifo_wr_en_0),
        .packed_fifo_wr_overflow_0(packed_fifo_wr_overflow_0),
        .packed_fifo_wr_sync_0(packed_fifo_wr_sync_0),
        .pcie_mgt_rxn(pcie_mgt_rxn),
        .pcie_mgt_rxp(pcie_mgt_rxp),
        .pcie_mgt_txn(pcie_mgt_txn),
        .pcie_mgt_txp(pcie_mgt_txp),
        .pcie_ref_clk_n(pcie_ref_clk_n),
        .pcie_ref_clk_p(pcie_ref_clk_p),
        .pcie_rst_n(pcie_rst_n),
        .peripheral_aresetn_0_0(peripheral_aresetn_0_0),
        .pkg_rd_addr(pkg_rd_addr),
        .pkg_rd_areq(pkg_rd_areq),
        .pkg_rd_data(pkg_rd_data),
        .pkg_rd_en(pkg_rd_en),
        .pkg_rd_last(pkg_rd_last),
        .pkg_rd_size(pkg_rd_size),
        .pkg_wr_addr(pkg_wr_addr),
        .pkg_wr_areq(pkg_wr_areq),
        .pkg_wr_data(pkg_wr_data),
        .pkg_wr_en(pkg_wr_en),
        .pkg_wr_last(pkg_wr_last),
        .pkg_wr_size(pkg_wr_size),
        .rx1_atten_0(rx1_atten_0),
        .rx1_b_atten_0(rx1_b_atten_0),
        .rx_clk_in_n_0(rx_clk_in_n_0),
        .rx_clk_in_n_1(rx_clk_in_n_1),
        .rx_clk_in_p_0(rx_clk_in_p_0),
        .rx_clk_in_p_1(rx_clk_in_p_1),
        .rx_data_in_n_0(rx_data_in_n_0),
        .rx_data_in_n_1(rx_data_in_n_1),
        .rx_data_in_p_0(rx_data_in_p_0),
        .rx_data_in_p_1(rx_data_in_p_1),
        .rx_frame_in_n_0(rx_frame_in_n_0),
        .rx_frame_in_n_1(rx_frame_in_n_1),
        .rx_frame_in_p_0(rx_frame_in_p_0),
        .rx_frame_in_p_1(rx_frame_in_p_1),
        .s_axis_ready_0(s_axis_ready_0),
        .temp_out(temp_out),
        .tx1_atten_0(tx1_atten_0),
        .tx1_b_atten_0(tx1_b_atten_0),
        .tx_clk_out_n_0(tx_clk_out_n_0),
        .tx_clk_out_n_1(tx_clk_out_n_1),
        .tx_clk_out_p_0(tx_clk_out_p_0),
        .tx_clk_out_p_1(tx_clk_out_p_1),
        .tx_data_out_n_0(tx_data_out_n_0),
        .tx_data_out_n_1(tx_data_out_n_1),
        .tx_data_out_p_0(tx_data_out_p_0),
        .tx_data_out_p_1(tx_data_out_p_1),
        .tx_frame_out_n_0(tx_frame_out_n_0),
        .tx_frame_out_n_1(tx_frame_out_n_1),
        .tx_frame_out_p_0(tx_frame_out_p_0),
        .tx_frame_out_p_1(tx_frame_out_p_1),
        .txnrx_0(txnrx_0),
        .txnrx_1(txnrx_1),
        .ui_clk(ui_clk),
        .up_enable_0(up_enable_0),
        .up_enable_1(up_enable_1),
        .up_txnrx_0(up_txnrx_0),
        .up_txnrx_1(up_txnrx_1),
        .user_lnk_up(user_lnk_up),
        .usr_irq_req_0(usr_irq_req_0));
endmodule
